Memory circuits, whether RAM, DRAM, SRAM or flash memory devices (and derivatives), are passive. Memory devices are essentially arrays of passive memory cells that store data from and retrieve data to a logic device. However, logic devices are typically used for specific applications. The memory components used in integrated circuits are largely inflexible and error-prone. Further, when a virus strikes a circuit, since the memory component is passive and static, the whole memory array is easily infected, thereby harming the logic circuit as well.
So far, earlier approaches have been limited to field-programmable memory built-in self-test (BIST) controller architecture models. These BIST models use algorithms to test a deterministic sequence of memory and are specifically designed to assist in testing memory defects. The programmable controller of a BIST system is only limited to diagnostic assessment of memory components and is thus both applied to passive memory circuits and narrow applications. These BIST systems apply merely inflexible pre-selected diagnostic algorithms to passive memory devices. They are not active and do not actively limit defective memory cell regions. These approaches do not actively modify memory configurations.
Field programmable memory devices exist. U.S. Pat. No. 5,914,906 describes a field programmable memory array consisting of memory sub-arrays and programmable features. However, this model does not change the configurability of the device like a field programmable gate array device. U.S. Pat. No. 6,501,111 specifies a three dimensional programmable device but the programmable memory features do not change their configuration but are merely programmed like a microprocessor. U.S. Pat. No. 7,160,761 describes a multilayer programmable nonvolatile memory device uses programmable features only to change the memory location of data, not to change the structure of the arrays in the memory device. The present invention advances the art.